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Bit
Name
Reset
Access
Description
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0
REGFREEZE
0
RW
Register Update Freeze
When set, the update of the Low Frequency clock control registers is postponed until this bit is cleared. Use this bit to update several
registers simultaneously.
Value
0
1
Mode
UPDATE
FREEZE
Description
Each write access to a Low Frequency clock control register is updated into the Low
Frequency domain as soon as possible.
The LE Clock Control registers are not updated with the new written value.
11.5.21 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0
(Async Reg)
Offset
0x058
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2
LCD
0
RW
Liquid Crystal Display Controller Clock Enable
Set to enable the clock for LCD.
1
LETIMER0
0
RW
Low Energy Timer 0 Clock Enable
Set to enable the clock for LETIMER0.
0
RTC
0
RW
Real-Time Counter Clock Enable
Set to enable the clock for RTC.
11.5.22 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0
(Async Reg)
Offset
0x060
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1
LEUART1
0
RW
Low Energy UART 1 Clock Enable
Set to enable the clock for LEUART1.
0
LEUART0
0
RW
Low Energy UART 0 Clock Enable
Set to enable the clock for LEUART0.
2011-04-12 - d0001_Rev1.10
115
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